Nandscape puzzles

Problems

Each puzzle gives you a goal, a gate budget, and sometimes a restriction on which blocks you have. Design inspired by leetcode.

15
Daily puzzle

BCD Invalid Code Detector

A 4-bit BCD digit only ever holds 0-9. Output HIGH when the 4-bit input W X Y Z encodes 10-15, a code that never appears in valid BCD.

Med.Solve →
0 / 53 Solved
TitleDifficulty

1. 2-Bit Equality Checker

Compare two 2-bit values (A1 A0 and B1 B0). XNOR is banned, so each bit's equality has to be built another way before combining them.

Med.

2. Single-Digit BCD Adder

Add two 4-bit BCD digits (0-9) plus a carry-in, producing a valid BCD digit and a carry-out. When the raw binary sum exceeds 9, correct it by adding 6.

Exp.

3. 4-to-1 Multiplexer (NAND only)

The same 4-to-1 multiplexer as before, SEL1 SEL0 choose between A, B, C, and D, but this time only NAND gates are on the palette.

Hard

4. 3-to-8 Line Decoder

A2 A1 A0 select one of eight output lines to drive HIGH; every other line stays LOW.

Hard

5. NOR from NAND

Build OR from NAND first, the way you just did, then invert it once more to get NOR.

Easy

6. 1-Bit Equality Checker

XNOR is banned since it would make this trivial. Output HIGH when A and B match.

Easy

7. 3-Bit Gray Code to Binary

Convert a 3-bit Gray code value back to binary. The top bit passes through, and every bit below is chained through XOR with the previous binary bit.

Med.

8. BCD Invalid Code DetectorToday

A 4-bit BCD digit only ever holds 0-9. Output HIGH when the 4-bit input W X Y Z encodes 10-15, a code that never appears in valid BCD.

Med.

9. 4-Bit Equality Checker

Compare two 4-bit values (A3 A2 A1 A0 and B3 B2 B1 B0). Output HIGH only when every bit matches.

Hard

10. Half Adder (NOR only)

NOR is also universal. Derive AND, OR, and NOT from NOR first, then produce SUM and CARRY for two bits.

Med.

11. 2-Bit Incrementer

Add 1 to a 2-bit number. COUT goes HIGH when the result wraps from 11 back to 00.

Med.

12. NOT from NAND

A NAND gate with both inputs tied to the same signal behaves like a NOT gate. Prove it.

Easy

13. 2-Bit Wide 2-to-1 Multiplexer

SEL picks between two 2-bit buses (A1 A0 and B1 B0) and routes the chosen one to Y1 Y0.

Med.

14. 1-Bit Magnitude Comparator

Compare two single bits with three separate outputs: LT when A is less than B, EQ when they match, GT when A is greater than B.

Med.

15. 2-Bit Ripple-Carry Adder

Add two 2-bit numbers plus a carry-in. Circuit blocks are disabled for puzzles, so the two bit-stages have to be wired by hand rather than reused as a block.

Hard

16. OR from NAND

De Morgan's law says A OR B equals NOT(NOT A AND NOT B). Invert both inputs, then NAND the results.

Easy

17. 4-to-2 Priority Encoder

Encode which of four request lines is active as a 2-bit binary index. When more than one is active, D3 outranks D2, which outranks D1, which outranks D0. Output 00 when none are active.

Hard

18. 1-Bit Greater Than

Output HIGH only when A is strictly greater than B.

Easy

19. Half Adder (NAND only)

Add two bits, producing SUM and CARRY as separate outputs, using only NAND gates.

Med.

20. 2-Bit Magnitude Comparator

Compare two 2-bit numbers (A1 A0 and B1 B0) with three separate outputs: GT, EQ, LT.

Hard

21. 3-Input Majority Voter

No gate restrictions, just a tight gate budget. Output HIGH when at least two of the three inputs are HIGH.

Easy

22. 3-Input Population Counter

Count how many of the three inputs A, B, C are HIGH and output the result as a 2-bit number (COUNT1 COUNT0, 0-3). This is exactly a full adder in disguise: think about what SUM and CARRY normally mean for three input bits.

Easy

23. 4-Bit Serial-In Shift Register

Build a 4-bit shift register. On each rising edge of CLK, SIN shifts into Q0 and every bit shifts up toward Q3. RESET clears all four bits immediately.

Exp.

24. 4-to-1 Multiplexer

Two select lines choose which of four data inputs reaches the output: 00 selects A, 01 selects B, 10 selects C, 11 selects D.

Med.

25. 1-Bit ALU: AND/OR Select

A minimal ALU slice. When SEL is 0, output A AND B. When SEL is 1, output A OR B.

Med.

26. Full Subtractor Without XOR

Subtract B and a borrow-in from A, producing DIFF and a borrow-out. XOR and XNOR are banned, so build the parity logic from AND, OR, NAND, and NOT.

Med.

27. Positive-Edge D Flip-Flop

Every other memory puzzle here is level-sensitive: transparent while an enable line is held high. Build a true edge-triggered D flip-flop instead, one that captures D only at the instant CLK rises from 0 to 1 and ignores it the rest of the time, with an async RESET that forces Q to 0. The standard technique is master-slave: two gated latches with opposite enables, so the second only ever sees a value the first has already locked in.

Exp.

28. 2-Bit Binary Multiplier

Multiply two 2-bit numbers (A1 A0 and B1 B0), producing a 4-bit product. Think in partial products and where their columns overlap, not repeated addition.

Hard

29. NAND from AND + NOT

NAND itself is off-limits this time. Build it the other direction, from a single AND and a single NOT.

Easy

30. Toggle (T) Flip-Flop

Build an edge-triggered toggle flip-flop. On every rising edge of CLK, Q flips if T is HIGH and holds if T is LOW. RESET clears Q to 0 immediately, regardless of CLK.

Hard

31. Full Adder

Add two bits plus a carry-in, no gate restrictions this time. Same problem as the NAND-only and NOR-only versions, just without the handicap.

Med.

32. Gated D Latch

Build a transparent, enable-gated D latch. While E is HIGH, Q follows D. While E is LOW, Q holds its last value.

Med.

33. 2-Bit Bitwise OR

OR two 2-bit buses together one bit position at a time, no carrying between bits.

Easy

34. Full Adder Without XOR

Add two bits plus a carry-in. XOR and XNOR are banned, so the parity logic must come from AND, OR, NAND, and NOT.

Med.

35. 3-Bit Binary to Gray Code

Convert a 3-bit binary number to its Gray code equivalent. Each Gray bit is the XOR of a binary bit and the one above it.

Med.

36. Perfect Square Lookup

Given a 2-bit number N (N1 N0, values 0-3), output N squared as a 4-bit number (SQ3 SQ2 SQ1 SQ0). A tiny lookup table: 0*0=0, 1*1=1, 2*2=4, 3*3=9.

Easy

37. 2-Bit ALU (AND / OR / ADD / SUB)

A tiny 2-bit ALU. OP1 OP0 select the function: 00 = AND, 01 = OR, 10 = ADD, 11 = SUB (two's complement). COUT only carries meaning in ADD/SUB mode.

Exp.

38. 4-Input AND

Output HIGH only when all four inputs are HIGH. The gate budget only allows one gate, so it won't fit as a chain of 2-input gates.

Easy

39. 2-to-1 Multiplexer

No gate restrictions, just a tight budget. Output A when SEL is 0, B when SEL is 1.

Easy

40. Half Subtractor

Subtract B from A for a single bit, producing DIFF and a BORROW flag when B is bigger than A.

Easy

41. 1-Bit Memory Cell

Build a circuit that remembers a single bit using two cross-coupled NAND gates. Inputs are active-low: pulse S low to set, R low to reset, and hold both high to keep the last value.

Easy

42. 4-Bit Ripple-Carry Adder

Add two 4-bit numbers plus a carry-in. Chain full adders the same way the 2-bit version does, just twice as long.

Exp.

43. AND from NAND

NAND is universal: every other gate can be built from it alone. Build a 2-input AND gate using only NAND gates.

Easy

44. 1-Bit ALU: Add/Subtract

A classic ALU trick: when MODE is 0, output A + B. When MODE is 1, output A - B using two's-complement (invert B and feed MODE in as the carry-in). COUT is the carry when adding, or the inverse of borrow when subtracting.

Hard

45. AND-OR Compound

Output HIGH when both A and B are HIGH, or when C is HIGH on its own.

Easy

46. Full Adder (NOR only)

Derive NOT, AND, and OR from NOR first, then build a full adder from nothing else.

Hard

47. BCD to Excess-3 Code

Excess-3 is a BCD digit's binary value plus 3. Build the adder that produces it for the 4-bit input W X Y Z.

Hard

48. 4-Bit Parity Without XOR

Output HIGH when an odd number of the four inputs are HIGH. XOR and XNOR are banned, so build parity as a sum of products instead.

Med.

49. Seven-Segment BCD Decoder

Decode a 4-bit BCD digit (D3 D2 D1 D0, values 0-9) into the seven segments of a display. Only the ten valid BCD codes are graded.

Hard

50. Sum-of-Products Warm-Up

Output HIGH when A and B are both HIGH, or when B and C are both HIGH. B is shared between the two terms.

Easy

51. XOR From Scratch

XOR and XNOR are off-limits. Build a 2-input XOR from AND, OR, NAND, and NOT.

Easy

52. Gated D Latch (NOR only)

Build a transparent, enable-gated D latch using only NOR gates. Derive AND, OR, and NOT from NOR first, then build the latch.

Hard

53. Hexadecimal Seven-Segment Decoder

Decode a full 4-bit hex digit (D3 D2 D1 D0, values 0-15) into the seven segments of a display, including the six hex digits A-F. Extends the BCD-only version to every possible input, so there are no free don't-cares left to simplify with.

Exp.