Implementation of a 2:1 Multiplexer Using Logic Gates
A 2:1 multiplexer picks one of two inputs and forwards it to a single output. A select line decides which. It is the hardware equivalent of a ternary expression: Y = SEL ? B : A.
Truth table
| SEL | Y |
|---|---|
| 0 | A |
| 1 | B |
Written out over all three inputs it is eight rows, but the behaviour compresses to those two lines: SEL chooses the source, and the unselected input has no effect on the output at all.
The boolean expression
Y = (A AND NOT SEL) OR (B AND SEL)
Step-by-step construction
Invert the select line
You need both SEL and NOT SEL, so start with a single inverter.
Two AND gates act as gates in the literal sense
AND A with NOT SEL, and B with SEL. Exactly one of these can be non-zero at a time, so one branch is always forced to 0 while the other passes its input straight through.
OR the branches
Since one branch is always 0, ORing them just forwards whichever branch is live. That is the output.
Why multiplexers matter
Selection is everywhere in hardware: choosing which register feeds an ALU, which result to write back, which instruction to run next. A multiplexer is also functionally complete on its own, which is why lookup-table based FPGAs can implement arbitrary logic from little more than muxes and memory.
Build it yourself
Four gates. Then try building a 4:1 mux from three 2:1 muxes, which is the standard way to scale it.