Implementation of an SR Latch Using NAND Gates
An SR latch is the smallest circuit that can remember a bit. Built from two cross-coupled NAND gates, it is the point where a circuit stops being a pure function of its inputs and starts having state.
What cross-coupled means
Each NAND gate's output is wired back into the other gate's input. That feedback loop is what stores the value: once the outputs settle into a stable pair, they hold it with no further input. Why this does not oscillate forever is worth reading if the loop bothers you.
The NAND version is active low
This is the detail that trips people up. In the NAND version the inputs are usually labelled S' and R', and they act when pulled low, not high. Holding both at 1 is the idle state where the latch remembers.
Behaviour table
| S' | R' | Q | Meaning |
|---|---|---|---|
| 1 | 1 | holds | Idle: the latch keeps its previous value |
| 0 | 1 | 1 | Set the stored bit to 1 |
| 1 | 0 | 0 | Reset the stored bit to 0 |
| 0 | 0 | invalid | Both outputs forced to 1, breaking the Q/Q' relationship |
Why S' = 0, R' = 0 is forbidden
Pulling both inputs low forces both outputs to 1, which contradicts the invariant that Q and Q' are opposites. Worse, when you release both at once the latch settles into whichever state wins a race, so the result is genuinely unpredictable rather than merely undefined on paper.
Where this leads
Removing that forbidden combination is what motivates the gated D latch, and making it update on a clock edge instead of a level gives you the D flip-flop, the element real registers are made of.
Build it yourself
Two NAND gates, cross-wired. Toggle the inputs and watch the output stay put when both return to 1.