The Gated D Latch: Controlling When Memory Updates

The SR latch's forbidden state exists because it hands you two independent levers, S and R, and trusts you never to pull both at once. The gated D latch removes that trust requirement by removing the second lever entirely.

One Data Input Instead of Two

There's exactly one data input, D, plus a second input, E (enable, sometimes labeled EN or drawn as a clock input). With only one data value in play, there's no longer any combination of inputs that could mean "do two contradictory things at once." The forbidden state isn't handled better here, it's structurally impossible to construct in the first place.

How D and E Become S and R

Under the hood it's still an SR latch. One NOT gate and two extra NAND gates sit in front of the same cross-coupled NAND pair from the SR latch's NAND-based cousin, deriving S and R from D and E. D feeds one gate directly and its inverse feeds the other, so the two derived signals can never both demand the same forbidden combination, they either disagree (an update) or both go inactive together (the safe hold case).

S = NAND(D, E)
R = NAND(NOT(D), E)

E = 0:  S = 1, R = 1  ->  SR latch holds (both NAND outputs forced high, no change)
E = 1:  S = NOT(D), R = D  ->  D drives Q directly through the latch

You're not learning a new primitive here, you're watching a disciplined way of driving the one you already have so the forbidden combination is never reachable.

Transparent vs. Holding

The whole behavior reduces to one rule worth memorizing exactly: while E is high, Q follows D immediately. This is called being transparent: the latch isn't storing anything yet, it's letting D pass straight through to Q, the same way glass lets light pass through. The instant E drops low, whatever Q happened to be showing at that moment freezes in place, and D can wiggle freely with zero effect on Q until E goes high again.

Try both halves of that rule on the circuit below. With E off, click D a few times and confirm Q never moves, the signal dies out partway through the gating logic instead of reaching the latch. Then turn E on and click D again: Q tracks it instantly, the same instant you toggle it, through the five real gates that make it happen.

Still Level-Sensitive

The gated D latch solves the forbidden-state problem, but it keeps one property from the SR latch that matters a lot once you start chaining these together: it reacts to a level, not a moment. "Transparent while E is high" means transparent for the entire stretch of time E happens to be high, which could span many gate delays, not one clean instant.

Why That's a Problem: Race-Through

Chain latches the way a shift register or counter needs to, latch A's output feeding latch B's input, with both sharing the same enable signal. While that enable is high, a change can ripple straight through A into B before E even has a chance to drop, data racing through multiple stages in a single "tick" instead of moving one stage at a time. Engineers call this race-through, and it's exactly why the next storage element exists.

The Fix: React to a Moment, Not a Level

What registers and counters actually need is a storage element that ignores D almost all the time and samples it at exactly one precise, vanishingly brief instant per clock cycle, so that chaining stage after stage moves data forward by exactly one step per tick with no possibility of racing through several stages at once. That's a D flip-flop, built by combining two of this exact gated D latch, not by inventing a new gate.