The SR Latch: Two Gates Remembering a Bit
Take two NOR gates. Feed the first gate's output into the second gate's input, and the second gate's output back into the first gate's input. That's it, no other components. This two-gate loop is the smallest circuit that can genuinely store one bit, and it's the direct application of the feedback idea from the previous tutorial.
Inputs, Outputs, and What "Stored" Means Here
Each NOR gate has one input left over after the loop is wired: those two free inputs are called S (set) and R (reset). The two gate outputs are Q and Q̄ ("Q-bar"), which are meant to always sit at opposite values. There is no separate memory cell hiding in this circuit. Whatever Q currently reads is the stored bit, nothing more than the value the feedback loop has settled into.
The Four Input Combinations
This version is NOR-based and active-high, meaning a HIGH on S or R is what triggers an action. That gives four cases:
S R | Q (next) Meaning
-------------------------------
0 0 | unchanged hold / memory
1 0 | 1 set
0 1 | 0 reset
1 1 | invalid forbidden stateS = 0, R = 0 is the interesting row: neither input is asking for anything, so the loop just keeps maintaining whatever it last decided. That row is the memory. S = 1, R = 0 forces Q to 1; S = 0, R = 1 forces Q to 0. S = 1, R = 1 is where things break, covered below.
The circuit below is real, not a diagram standing in for one: two NOR gates wired exactly as described, running the same gate-evaluation logic the underlying simulator uses everywhere else. Click S or R and watch the signal propagate through the loop.
Why S = 1, R = 1 Is Forbidden, Not Just Undefined
"Undefined" would mean the designer chose not to specify a behavior. This case is worse than that: it's structurally impossible to give it a sane behavior at all. With S = R = 1, both NOR gates are being actively driven to output 0, which directly contradicts the premise that Q and Q̄ are supposed to disagree. They don't, they're both 0.
The real trouble shows up when you release the inputs back to S = 0, R = 0. Both gates are now trying to climb back out of that invalid state at the same time, and which one wins, meaning which value Q settles into, depends on microscopic differences in gate delay that no schematic captures. Two supposedly identical latches on the same board can resolve this race differently. There's no clever rewiring that fixes this while keeping two independent inputs; removing the ambiguity means removing the ability to set both flags at once, which is exactly what the next tutorial does.
One Idea, Two Common Flavors
Two cross-coupled gates holding a bit through feedback is the seed every other storage element in this section grows from. The NOR-based, active-high version above is the clearest one to reason about first. A second, equally common variant swaps in NAND gates and flips the inputs to active-low: pulse S low to set, pulse R low to reset, hold both high to remember. You'll find that exact variant built from real NAND gates in the sandbox's default circuits.
What's Next
An SR latch requires whoever is driving it to keep S and R mutually exclusive by hand, forever, or risk the forbidden state. The gated D latch removes that burden by giving you exactly one data input, so there's no combination of inputs left to forbid.